Clocks and Clock Cycles Latches and Flip-flops Registers and Register Files SRAM DRAM Synchronous Memories Memory Hierachy Main Objectives of a Memory Hierarchy Principles of Locality Memory Hierarchy Rules: Direct-Mapped Caches Calculating Cache Size Spatial Locality and Multiword Cache Blocks Mapping an address to a multiword cache block Performance Issues with Multiword Blocks Handling Cache Misses Handling Instruction Misses Handling Data Misses Handling Cache Writes Write Miss in a Single-Word Block Cache Combined Data and Instruction Caches Versus Separate Caches Handling Writes in Multi-word Blocks Designing Memory to Support Caches Memory Organizations Measuring and Improving Cache Performance Effects of changes to architecture on performance 1. Increasing Processor Speed 2. Increasing Clock Rate Average Memory Access Time (AMAT) Reducing Miss Rate by Flexible Placement of Blocks Set associativity Fully associative caches Reduction in Miss Rate Locating a Block in the Cache Cost of Cache: Number of Comparators and Tag Bits. Block Replacement Policy Multilevel Caches Virtual Memory Paging and Caching: An Analogy Address Translation Design Choices Page Placement and Faults: Finding Pages Write-Back Policy LRU Page Replacement Page Table Implementations (first three in notes) Calculating Size of Page Table